MOL (Multi-Optical Links)

The card is a PCIe 8 lanes card.

This card sites 4 SFP working @ 8Gb/s and 1 SFP+ @ 10Gb/s.

The Stratix IV FPGA is the center of the card on which DDR2 , QDR+, SFP and PCIe are connected.

The preliminary schematic is here. Requirements for routing.

The time scale. PCB, Documents EDMS.

The design turn around the  PCIe bus. Internally this bus works with single access where a Reset,Clock(250 MHz),CS(active H), Func(x),dataW(32),Wr_ena (active H),dataR(32),Rd_ena(active H) and Data_ready(Active H).

The design is devided in 5 blocks, PCIe, Gb(4 links up to 8Gbit) , 10 Gb link, QDR and DDR2. Each of them has is own CS and 2048 functions.

PCIe is the Altera HardCore

Gb is designed to work with the HCAL AMC13 (5Gb) where a simple protocol with a downstream flowto to transfert data from AMC13 to MOL(with acknowledge) and a up-stream to transfer command (read/write) to the AMC13 SLINK-block.