Block diagram

The FRL has a primary PCI bus : CompactPCI 32-bit 33MHz. The extension of this bus to 64-bit or 66MHz, imply an additional cost on the FPGA, the controller and the back-plane.

There are two FPGAs on the CPCI FRL:

• Bridge PCI
• FRL function

-Bridge PCI is impementing in a FPGA (APEX 20K100 FBGA) mainly because the primary PCI bus is 33MHz and the secondary PCI bus is 66MHz.This kind of bridge does not exist on the market. This FPGA will have its own EEPROM for configuration. This will give the independence between FRL function and PCI bridge.

-FRL FPGA (Stratix 10 FBGA) needs a bigger eeprom for configuration. This EEPROM is able to keep up to 8 possible configurations. Form the bridge FPGA, 3 lines (controlled by PCI) will define which configuration the user want to download in the FRL function FPGA.

For the spare IOs between FPGAs, pins or pads will be implemented to able debugging or to add some external wires.

JTAG : the jtag will be controlled trough a connector or (like the GIII) through the PCI configuration of the bridge.

Memory: SRAM or SDRAM.

The choice have to done about the capacity.

• With SRAM the maximum is 4MBytes for two chips. But the control is much simple and there is no clock cycle losed (refresh, CAS, RAS.....)
• With the SDRAM the capacity used can be 32 MBytes. But the control is complex, some clock cycle is losed for refresh, and each time we access the memory (CAS< RAS,...) then this memory is not useful for single data access (statistic implementation)

The hot-swap function won't be implemented. This introduce complexity in software and hardware. And this function is not need for our use.