FRL (FED Readout Link)

The FRL is a compactPCI card as shown by the picture below

Installation

The production (650 FRLs and 720 Slink) was tested and is installed in the USC55 at Cessy (end 2006)

The document relative to the engineering is here.

 

Schematic (version 3)

          Up to this version the SVF file for the main FPGA (ALTERA Stratix)  should have a name starting with "p4_frl_frl_f020...."

Schematic (version 4) EDMS page (Modif , Ferrite + control the Power_down pin of the LVDS chip)

          For this version the SVF file is different from the previous version for the  main FPGA, it should start with "p4_frl_frl_f021...."

          A label on the front panel indicates if the board is version 2 

 

Documents relatives to the production are:

    Specification(pdf) ; layout specif(pdf) ; pcb_layers (pdf) , gerber-files,

The board is built with extra parts of PCB : Mechanical (PDF)

 

Documents to solder components

    top_layers(pdf); bottom_layers(pdf); components_list(xls), fichiers.faz, Other_files

This preserie is planned to be ready for beginning of next year.


CMC Transmitter

 

Associated to the FRL board, there is a CMC (Common Mezzanine Card) that will be plugged on the FED boards.

The both boards (FRL and CMC) will be connected together with a cable using the LVDS (Low Voltage Differential Signaling) technology.

 

Schematic (version 2)

         Up to this version the SVF file for the FPGA (ACEX)  should have a name starting with "p2_cmc_cf01...." 

Schematic (version 3) EDMS page (Ferrite + more back control + control Power_down & DC_ON/OFF of the LVDS chip)

          For this version the SVF file is different from the previous version for the FPGA, it should start with "p2_cmc_cf11...."

          A label on the front panel indicates if the board is version 2 

 

Documents relatives to the production are:

     Specification (pdf); pcb layers (pdf); gerber-files

 

Documents to solder components

    top_layers(pdf); bottom_layers(pdf); components_list(xls) ,fichiers faz, Other_files

 

An optical version is under development (should be ready for May2017)

The EDMS documents can be found here: http://edms.cern.ch/nav/EDA-03555-V1-0

 

 


Documentation

 

SLINK64 Specifications (1) (2) . Some differences with the original specification are explained here

FRL manual ver5

Test bench II software preliminary  (frl-0.1a.pdf)

 

The DAQcolumn informations usefull for software part are detailled here.

Production (FRL_Vx, CMC_v1-2, FMM, TD) database http://cms-project-daq-frltest.web.cern.ch/cms-project-daq-frltest/

Production (CMC_optic) database https://cms-frl.web.cern.ch/cms-frl/CMC_opt_db/search.php/

Hardware intervention to exchange pieces

Test bench column in LAB 40 -2 and -3

Lab 2

Lab3

 

If you have any question contact Dominique Gigi CERN EP/CMD